Photos

General overview of the preliminary proposed Smart Meter

Based on a Zynq-7000 FPGA as core, it includes an Analog Front-End (ADE9153A), as well as the necessary Wi-Fi connectivity.

Electrical circuit of the proposed AFE for acquiring voltage and current up to 100k HzGeneral overview of the preliminary proposed Smart Meter

Architectures proposed for the classification of electrical loads based on events

Block diagram of the msart meter designed for mid frequencies (up to 4 kHz)

Assessment of sleeping activity for a household from a dataset

Display of daily activity monitoring for a household involved in the experimental tests